In microelectronic device manufacturing, a bare microelectronic integrated circuit (IC) die, or chip, is often coupled directly to a host printed circuit board (PCB) or first coupled to a host electronic package, which in turn is coupled to a host PCB. The package serves to protect the die and can provide a standardized interface between the die and the system in which it will be used. The packaged IC die is subsequently mounted to a PCB, such as a daughterboard or a motherboard in a computer system or the like.
One common technique for packaging an IC die involves mounting the die on a die attach pad of a leadframe having leads that extend outward from one or more sides of the die attach pad. This is typically the case for plastic and some ceramic packages. In some other ceramic packages, the leadframe is attached to the exterior of the ceramic package body and the die is attached and wire bonded to pads connected to the external leadframe. When mounted to the leadframe, the back of the die is electrically connected to the die attach pad and the front peripheral bond pads of the die are connected to the leads of the leadframe by bond wires which provide a mechanically compliant connection that is not affected by thermal expansion and contraction of the package body, leadframe, and die.
Generally, a peripheral bond wire interface between an IC die and a host package or PCB is compliant, but an interfacial bond between a flip-chip die and a host package or PCB is usually not. This is because the short aspect ratio (ratio of length divided by cross-sectional area) of the interfacial connections between a flip-chip die and a host package or PCB cause them to be very stiff and not very tolerant of thermal coefficient of expansion (TCE) differences between the die and package or PCB material or of any interfacial interface distortions due to flexure of the package or PCB from acceleration, mechanical shock, vibration, or the like. The same is generally true of short interfacial connections between an electronic package and its host PCB.
Ultimately, the leadframe and die are encapsulated with a ceramic or plastic material so that the leads of the leadframe extend out of the package and are accessible. One common through-hole package is known as a dual-in-line package (DIP), which is rectangularly shaped with an equal number of leads extending from two opposite sides. Dual flat pack (DFP) and quad flat pack (QFP) are common surface mount technology (SMT) packages and are typically rectangular or square having planar leads distributed around their periphery on two opposite or all four sides, respectively. As to the encapsulation materials, ceramics are usually used, where reliability and a hermitic seal are required such as for military and space qualified applications. Plastics are usually used for commercial products where it is desired to minimize cost and where a hermetic seal is not required such as for consumer, automotive, and industrial applications.
An electronic package including a die can then be bonded or otherwise electrically, thermally, and/or mechanically attached to a printed circuit board. Typically, a surface-mount technology assembly process is used which involves attaching the leads (and optionally the body) of the package to attach pads on the surface of the printed circuit board. Solder, conductive and/or non-conductive polymers are typically used. The leads are typically attached by screen-printing solder or polymer paste onto the attach pads, positioning the leads of the package relative to the attach pads, and then reflowing the solder by a vapor phase or infra-red reflow technique or curing the polymer paste in a oven. The attach pads of the printed circuit board are connected to traces or wires that provide a mechanical, thermal, and/or an electrical connection to other integrated circuits or electronic devices.
As technology has advanced, the size and circuit density of microelectronic integrated circuit chips have increased and the number of leads used in connecting such chips has correspondingly increased. This trend is expected to continue. Using conventional bond wire and packaging techniques with peripheral leads, the package footprint area (proportional to the product of length and width) increases faster than the lead count (proportional to the sum of length and width). This results in a reduction of the interconnect density with increasing lead count in peripheral leaded packages. To overcome this problem, as illustrated in FIG. 1, a chip device 10, such as a bare (e.g., flip chip) or packaged device, is connected to a printed circuit board 12 by using an interfacial connection area array 14 rather than extending peripheral bond wires or leads as described above. Area array device packages include ball grid arrays (BGAs), land grid arrays (LGAs), and column grid arrays (CGAs), for example, and may comprise regular grids or irregular arrays. The area array 14 provides a means of mechanically attaching a bare or packaged chip device 10 to a printed circuit board 12. Additionally, the area array 14 provides a means of electrical and/or thermal interconnection between an attach pad 16 of a package or printed circuit board 12 and an attach pad 18 of a bare or packaged chip device 10. Typically, solder or polymer bumps or balls comprise the interfacial connection area array 14 of the bare or packaged chip device 10. The area array 14 of the bare or packaged chip device 10 is then aligned with the attach pads 16 of the printed circuit board 12 and bonded in place. In this way, an interfacial area array interconnect increases interconnect density and reduces bare or packaged device size. Unlike peripheral leaded packages, the interconnect density of area array packages remains fairly constant with increasing interconnect counts.
Although the use of an interfacial area array to interconnect a bare or packaged chip and a package or printed circuit board overcomes the space issues noted above, the interfacial solder joints connecting these area arrays are more susceptible to thermal coefficient of expansion mismatch than with conventional peripheral bond wires or package leads. The relative displacement between a pair of mating attach pads is proportional to their distance from a neutral point at the center of the array, the TCE difference between the mating surfaces, and the temperature. This problem is particularly noticeable as the size of the area array increases. When undergoing thermal cycling, the TCE mismatch between the bare die and the package and/or between the package and the printed circuit board produces stress on the solderjoints of the area array(s). This stress can cause microcracks to form in the joints, which eventually causes them to fail. Moreover, such microcracks can arise from stresses caused by distortions of the interfacial interface due to acceleration, mechanical shock, or vibration.
Plastic packages used in commercial products exhibit a thermal coefficient of expansion close to that of a standard epoxy-based printed circuit board material, which is approximately 17 parts per million. As a result of such a close thermal coefficient of expansion match, a plastic package integrated with a printed circuit board, on average, can routinely withstand 4-5 thousand thermal cycles between minus 40 degrees Celsius and 125 degrees Celsius prior to failure of an interconnection. Conversely, ceramic packages exhibit a thermal coefficient of expansion of approximately 7 ppm. This causes a large thermal coefficient of expansion mismatch between a ceramic package and printed circuit board. Such mismatch causes stresses that can reduce the reliability of an interfacial interconnection between a ceramic package and printed circuit board to 100 thermal cycles or less.
Several different techniques have been developed to improve the reliability of ceramic packages. For example, crack resistant alloys have been developed. However, these alloys only improve reliability to 200-400 cycles. Also, solder columns that are 3-4 times taller than conventional solder balls have been used. This allows the joints to flex and absorb some of the stress so that the package can withstand upwards of 1000 thermal cycles. However, the solder columns are very fragile and susceptible to breakage during packaging, handling and assembly. In another approach, printed circuit boards have been fabricated with a metal core to help to reduce the thermal mismatch. However, these printed circuit boards are expensive to produce and suffer from other problems related to their ability to reflow solder. Ceramic boards can be used but are limited in size and are also very expensive. All of the above address compliance in the X-Y plane (parallel to the die, package and PCB planes) to accommodate TCE mismatch. None of the above address the Z axis compliance (perpendicular or normal to the die, package and PCB plane) needed to accommodate distortions of the interfacial area array interface such as printed circuit board flexure due to acceleration, mechanical shock and vibration.
As illustrated in FIG. 2, one technique for managing a large thermal mismatch between a bare or packaged chip 20 or other electrical component and a package or printed circuit board 22 is to use an interposer 24. The interposer 24 is positioned between the bare or packaged chip 20 and the package or printed circuit board 22 and generally comprises a flexible substrate 26 and first and second area arrays, 28 and 30, on each side of the substrate 26. The area arrays 28 and 30 provide an electrical connection from one side of the substrate 26 to the other. This is done by electrically connecting an attach pad of the first area array 28 on one side of the substrate 26 with a corresponding attach pad of the second area array 30 on the other side of the substrate 26. The area array 28 is connected to attach pads 32 of the package or printed circuit board 22 and the area array 30 is connected to attach pads 34 of the bare or packaged chip 20. In this configuration, when the bare or packaged chip 20 undergoes thermal cycling, thermal expansion stresses are absorbed by the flexible substrate 26 rather than being transferred to solder joints in an array. In this way, the vertically stacked connection arrays can flex to absorb relative X-Y plane TCE displacement between the attachment surfaces like a column grid array.